Latent-Defect Screening
Reducing Burn-in Time
through High-Voltage Stress
Test and Weibull Statistical
Analysis
Mohd Fairuz Zakaria and Zainal Abu Kassim
Melanie Po-Leen Ooi and Serge Demidenko
Freescale Semiconductor
Monash University
nents.1-3 Thus, the process screens for (or
eliminates) marginal devices, those with
inherent defects, and those with defects
resulting from manufacturing aberrations—all time- and stress-dependent failures. Proper burn-in test conditions
provoke early failures of weak devices,
screen out those with excessive parametric drift, and improve manufacturability.
The graph of a typical device’s failure characteristics
takes the form of a classical bathtub curve, as in Figure 1.1,2
The rapidly decreasing dotted curve in Figure 1 represents
what we call infant mortality—parts that fail because of
manufacturing defects, foreign particles, design errors, and
other problems not caught during initial tests at the probe
(wafer) level. The central, flat part of the graph shows the
steady state of device operation with a constant (and normally low) failure rate. The device remains in this period
for the rest of its useful life. When the device reaches the
wear-out stage, the parts fail from overuse or fatigue.
Manufacturers usually specify the product’s lifetime as ending well before the wear-out stage.
With burn-in, the manufacturer stresses the devices
under conditions that accelerate infant mortality, reducing the length of time necessary to detect these unreliable parts. The solid-line curve in Figure 1 represents this
phenomenon. The “Types of burn-in” sidebar describes
the various methods of burn-in currently in use.
Editor’s note:
High-voltage stress testing (HVST) is common in IC manufacturing, but
publications comparing it with other test and burn-in methods are scarce.
This article shows that the use of HVST can dramatically reduce the amount
of required burn-in.
—Phil Nigh, IBM Microelectronics
TO GUARANTEE an industry standard of reliability in
ICs, manufacturers incorporate special testing techniques
into the circuit manufacturing process. For most electronic devices, the specific reliability required is quite
high, often producing a lifespan of several years. Testing
such devices for reliability under normal operating conditions would require a very long period of time to gather
the data necessary for modeling the device’s failure characteristics. Under this scenario, a device might become
obsolete by the time the manufacturer could guarantee
its reliability.
Manufacturers can gather reliability data more quickly by using accelerated testing, which shortens the timeto-failure process without changing the device failure
characteristics. Among the most widely used accelerated testing methods in the electronics industry is burnin, the process of stressing electronic devices for a
specific time period under stress conditions such as elevated temperature and voltage. Manufacturers first used
the method in the 1960s during early, low-volume production to screen out immature parts, and it soon
became a military standard.1-3
Burn-in works by triggering failure in an IC’s defective components without damaging the good compo-
88
0740-7475/06/$20.00 © 2006 IEEE
Drawbacks of burn-in
A properly arranged burn-in screens out the weak
devices, thus improving the quality and reliability of the
Copublished by the IEEE CS and the IEEE CASS
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Burn-in reduction
methodologies
To counter these cost and time problems, researchers have proposed several
methods to reduce or eliminate burn-in.
Among the most efficient are methods
based on IDDQ testing (for circuits implemented in CMOS technology), statistical
methods, and high-voltage stress testing.4-6
Detailed studies have shown that for particular devices, IDDQ testing—with proper
vector selection—can eliminate the need
for burn-in.4,5,7 However, the method is
effective primarily for wafer-level testing
and may work poorly at the package
level.7 Because our study concentrates
solely on packaged devices, we will
leave aside IDDQ and focus instead on two
March–April 2006
Infant mortality
Wear-out
stage
Steady state
Failure rate
shipped population as a whole. However,
the test itself does not actually improve
the quality or the reliability of the circuits.1 Indeed, under the wrong burn-in
conditions, the test can actually wear out
or even damage the parts being tested.
For example, burn-in raises the junction
temperature of semiconductor devices.
This results in an increase in their leakage
currents, which can cause thermal runaway, and this in turn can reduce manufacturing yield.
A second problem is that although
burn-in is a form of accelerated testing, it
is still very time-consuming. For some
devices, burn-in requires many hours—
in fact, hundreds for military-grade ICs.3
On top of that, additional procedures
must take place between burn-in sessions. Thus, burn-in can consume as
much as 80% of the total product testing
time, becoming the bottleneck of the
entire IC manufacturing process.
Finally, the burn-in process incurs
high capital costs. Each burn-in board
can house only a limited quantity of ICs;
each burn-in chamber, a specific number of boards. If a particular device is in
great demand, a manufacturer might
have to make a costly investment in
more burn-in boards and chambers.
1,000 hours
With burn-in
25 years
Without burn-in
Figure 1. The classical bathtub curve and the effects of burn-in.
Types of burn-in
Before shipping to customers, assembled ICs undergo several types of
extensive testing. A typical test flow includes pre-burn-in testing, monitored
burn-in testing, and ATE final testing. Burn-in, accelerated testing performed
under elevated temperature and other stress conditions, currently serves as
a quality improvement process that tests the operation of a device after fabrication and prior to more comprehensive final parametric and functional tests.
The electronics industry uses four main types of burn-in: static, dynamic,
monitored, and test-in burn-in or TIBI. (TIBI is also often called in situ burnin.) Table A summarizes the essence of these four methods. Figure A gives
illustrations.
Table A. Types of burn-in.
Type
Static
Input/output
No I/O, read point
at test
Description
Device stressed at constant and
elevated temperature for an extended
period of time
Dynamic
Stimulus input,
read point at test
Monitored
Stimulus input and live
output, read point at
Similar to static, but with test vectors
to toggle internal nodes of the device
Identifies failed units and separates
them from good devices
burn-in and test
TIBI
Stimulus input and
A combination of functional and burn-in
responsive output,
testing; functional input patterns
read point at burn-in
applied and output responses
observed
89
Latent-Defect Screening
methods that can reduce burn-in time at the package
level: the Weibull statistical method and high-voltage
stress testing (HVST).
Weibull statistical analysis
The Weibull distribution, which models time-dependent failure data, sees wide use in engineering primarily
because it can accommodate a wide variety of phenomena. We can easily use it to model most failure distributions over a significant range of time. By calculating
its variables (m, the Weibull slope or shape parameter;
and c, the characteristic life-scale parameter) and computing the cumulative distribution function (CDF), we can
obtain the distribution that best describes a set of failure
data; this lets us make predictions about future failures,
including the number of parts expected to fail.
To derive the Weibull CDF F(t), we first consider a
hazard function H(t), which describes the probability
of failure during a small increment of time with the generalized failure rate λ:8
H(t) = (λt)m
Using basic identity to relate F(t) to H(t), we find
F(t) = 1 – exp[–H(t)] = 1 – exp[–(λT)m)]
By substituting c = 1/λ, we obtain the Weibull CDF as
follows:
⎡ ⎛t⎞
F (t ) = 1 − exp ⎢ − ⎜ ⎟
⎢ ⎝c⎠
⎣
m
⎤
⎥
⎥
⎦
Here, t is the variable (usually lifespan) and c is the
characteristic life-scale parameter. Changing the life-scale
parameter while keeping all other parameters constant
will stretch the distribution curve. In addition, the value of
the life-scale parameter determines the area of the life
span of the device: where c < 1 describes infant mortality
stage, c = 1 describes constant failure rate, and c > 1
describes rapid wear-out (similar to the bathtub curve).
When the Weibull slope or shape parameter, m, is 1,
the equation yields an exponential constant failure
rate; when m is greater than 1, it yields a polynomial
failure rate.
High-voltage stress testing
The basis for HVST is that elevated temperatures may
not necessarily stress certain devices (for example,
90
those with leaky gate oxide); hence burn-in for those
devices is a needless process. In contrast, some devices
might actually require HVST for guaranteed reliability.4
However, using HVST by itself might not reliably
screen defects such as heavy-metal contamination of
wafers. HVST is also unsuitable for testing CMOS ICs with
large, embedded nonvolatile memory—such as flash
memory—and devices with an internal voltage regulator but no onboard circuit to disable the regulator.6 Also,
HVST doesn’t detect failures that are only thermally activated; the elevated voltage applied during HVST might
even temporarily correct these types of failures.
Therefore, burn-in is still necessary for most ICs produced, especially those destined for mission-critical
applications, which have very low parts per million
(PPM) requirements. (PPM is an industry-standard measure of reliability. It refers to the number of devices
allowed to fail per one million parts shipped to the customer. Different ICs have different PPM standards,
depending on their intended usage.) For devices with
less-stringent PPM requirements, HVST has proven successful in reducing burn-in duration.6
The main goal of our research has been to reduce
burn-in time by combining the application of HVST with
the Weibull statistical analysis modeling of a device’s
failure characteristics. Successful implementation of this
plan will yield a new test flow that is much shorter than
the traditional one and does not sacrifice IC reliability.
Burn-in test time reduction: A step-bystep approach
Figure 2 outlines our burn-in reduction plan, combining HVST and Weibull statistical analysis. For the technology parameters of the device we used for our research
(such as gate-oxide thickness), we chose appropriate
models based on the JEDEC standards JESD749 and
JEP122,10 and we developed our burn-in reduction
methodology based on these models. (The JEDEC Solid
State Technology Association, once known as the Joint
Electron Device Engineering Council, is the semicon-
ductor engineering standardization body of the
Electronic Industries Alliance, EIA.)
Stage 1: Determine old burn-in parameters
Burn-in shortens the time required for weak devices
to fail during nominal (operating) conditions tN by
stressing parts at an acceleration factor A. The main goal
of stage 1 of our research was to obtain the acceleration
factors of the monitored burn-in process before attempting any burn-in reduction. The following equation
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describes the relationship between acceleration factor
A, the time to failure under stress (burn-in conditions)
tS, and the nominal time to failure tN:
Start: Burn-in reduction goal.
tN = A(tS) × tS
Stage 1: Determine duration for old (traditional) burn-in.
To reduce the burn-in test time while providing the
required level of defect screening, we must make the
test-stress parameters harsher. That is, we must apply
either higher voltages or higher temperatures, or both.
Hence, we need first to calculate acceleration factor A
for the burn-in conditions. For oxide-related failures, A
for time t0 is the voltage acceleration AV(t0) multiplied
by the temperature acceleration AT(t0):8
Stage 2: Find new voltage acceleration parameter.
Stage 3: Develop HVST program.
Stage 4: Plan burn-in experiment.
A(t0) = AT(t0) × AV(t0)
Stage 5: Validate HVST effectiveness.
Temperature acceleration AT follows the Arrhenius
equation:2,8
Stage 6: Apply Weibull analysis to data.
⎛E ⎡ 1
1 ⎤⎞
−
AT (t 0 ) = exp ⎜ a ⎢
⎥⎟
⎝ k ⎣ TN (t 0 ) TS (t 0 ) ⎦ ⎠
Conclude: Obtain duration for new burn-in.
Here, Ea is the activation energy dependent on the
type of device (eV); k is Boltzmann’s constant (8.62 ×
105 eV/K); and t0 is initial time to failure under stress
conditions.
For the given implementation technology and parameters of the device under test, we model the voltage
acceleration AV as9,10
AV(t0) = exp(PVA[VS(t0) – VN(t0)])
(1)
Here, VS is the gate voltage under stress (burn-in)
conditions; VN is the gate voltage under nominal (operating) conditions; PVA is the parameter for voltage acceleration (1/V). We derived the voltage acceleration
values, listed in Table 1,8 from acceleration experiments
done at the package level at the semiconductor manufacturing company. The other parameters come from
the device specifications sheet.
Depending on the parameters of circuit implementation and the specifics of the device, other voltage
acceleration models presented in the literature might
also be appropriate.11,12 However, in general, reliable
voltage acceleration models to follow can be found in
JEDEC industry standards.
Table 2 shows the calculated acceleration factors for
the device we used in our research.
March–April 2006
Figure 2. The burn-in reduction methodology.
Table 1. Voltage acceleration parameters.
Nominal core voltage (V)
PVA (1/V)
5.0
2.8
3.3
3.0
2.5
4.5
1.8
5.9
1.5
7.4
1.2
8.0
Table 2. Calculated acceleration factors.
Acceleration factor
Voltage acceleration on power supply 1
Burn-in conditions
43.01 V
Voltage acceleration on power supplies 1 and 2
18.65 V
Temperature acceleration factor, AT
70.6
Voltage acceleration factor, AV
Total acceleration factor, A
43
3034.6
91
Latent-Defect Screening
Table 3. New burn-in conditions based on the desired
1. Identify HVST pattern list for target device.
burn-in duration.
Parameter
Value
Desired burn-in duration, t1
3 hrs.
Voltage of power supply 1
4.342 V
Voltage of power supply 2
2.642 V
2. Integrate HVST flow into existing test program.
3. Characterize device and select voltage levels.
Stage 2: Find new voltage acceleration
parameter
4. Find duration for HVST pattern list execution.
The acceleration factor we’ve talked about so far
refers to the acceleration (over the nominal time to failure) achieved by burn-in testing with the stress duration
of t0 hours. In this particular case, t0 is 12 hours. To
reduce the burn-in time to some target duration of t1
hours (for example, 3 hours), we can increase the burnin voltage supply without affecting the burn-in temperature; that is, we increase AV and leave AT unchanged.
Thus, Stage 2 of our research involved calculating the
new voltage acceleration factor AV(t1).
The nominal time to failure tN is constant. If we
increase burn-in duration from t0 to t1 hours
tN = A(t0) × t0 = A(t1) × t1
∴A(t 1 )=t 0 /t 1 ×A(t 0 )
A V (t 1 )×A T (t 1 )=t 0 /t 1 ×A(t 0 )
Holding the temperature acceleration AT(t) constant,
AT(t0) = AT(t1)
∴A V (t 1 )×A T (t 0 )=t 0 /t 1 ×A(t 0 )
AV ( t 1 ) =
t0
t1
A(t 0 )
AT ( t 0 )
(2)
For example, if the original burn-in duration t0 is 12
hours, and we identify the desired burn-in duration t1 as
3 hours, with unchanged burn-in test temperature,
AV ( t 1 ) =
t0
t1
AV ( t 0 ) × AT ( t 0 )
AT ( t 0 )
Thus,
AV ( 3 ) =
12
AV (12 ) = 4 AV (12 )
3
We can find the burn-in voltage that satisfies the
desired burn-in duration by solving equations 1 and 2:
⎛ 1 ⎞ ⎛ t0 ⎞
VS ( t 1 ) = VS ( t 0 ) + ⎜
ln
⎝ PVA ⎟⎠ ⎜⎝ t1 ⎟⎠
92
5. Validate efficiency/residual infant mortality.
6. Validate long-term reliability.
Figure 3. HVST implementation plan.
Here, VS(t1) is the new gate voltage under stress
(burn-in) conditions; VS(t0) is the previous gate voltage
under stress (burn-in) conditions; t1 is the new burn-in
duration; t0 is the previous burn-in duration; PVA is the
parameter for voltage acceleration (1/V), from Table 1.
Table 3 summarizes the results we obtained by completing stage 2 of our research.
Stage 3: Develop the HVST program
This stage of our burn-in reduction plan took great
care; successfully developing and incorporating HVST
into the existing testing process required us to add several pre- and post-test steps. Figure 3 shows the process.6
A good HVST test pattern should provide maximum
fault coverage in the shortest time possible. For
instance, functional test patterns might not be as effective as patterns using the device’s DFT features in terms
of nodal coverage. In the case under discussion, the
device manufacturer data recommended using test patterns including those employing the device’s BIST features and circuitry, and core and system dc scan-test
patterns. (A detailed description of the test patterns is
outside the scope of this project, so we won’t discuss or
characterize them here.)
For this research, we chose the following HVST
patterns:
■
core dc scan, which tests the circuitry in the core of
the chip using the embedded scan path;
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■
■
■
system dc scan, which tests circuitry in the rest of the
chip using the scan path;
array BIST (ABIST), which tests embedded memories in the chip using BIST circuitry; and
Motorola BIST (MBIST), which tests circuitry outside
the core that is related to the peripheral memory and
the rest of the system.
It’s possible to integrate HVST into an existing test
flow at two stages of the manufacturing process: wafer
level or IC package level. We implemented HVST at
package level, at the final test stage. (We are considering adding HVST also to the wafer-level through finaltest-to-probe correlation.) Before implementing HVST,
device characterization is an important step. Although
HVST includes functional tests, fail flags must not be set
if a device fails. This is because, at the elevated voltages,
the IC might not meet its timing specifications although
it is actually functioning. If a device fails during HVST,
it should be retested later at nominal voltages to confirm the functional failure.
For optimum reliability, voltage levels should be as
aggressive as possible to minimize the test duration
without inducing permanent damage in the IC. Ideally,
the voltage level should be about 80% of the chip’s
breakdown voltage. However, an IC’s breakdown voltage is normally unknown and not specified by the
datasheet; thus, we first had to characterize the device.
To determine the device’s VDD(I/O) and VDD(core) breakdown supply voltages, we used several devices that
were known good units (KGUs). We began the process
by first setting the voltages to their maximum specifications. As long as a chip did not fail, we increased both
supply voltages by 100 mV and retested the KGU. When
the chip failed, we noted the supply voltages at the time
of failure as the initial breakdown voltages (A1 and A2
for I/O and core, respectively), and labeled and saved
the KGU. (Figure 4 diagrams the process.) We then
repeated this flow with another KGU to verify the result.
After finding the initial breakdown voltages, our next
step was to characterize the breakdown voltage for VDD(I/O)
for the device’s I/O circuitry (see Figure 5). We set both
voltages VDD(I/O) and VDD(core) to 300 mV below the initial
breakdown values A1 and A2, respectively. Then we tested
another KGU using the pattern list, incrementing the
VDD(I/O) by 100 mV each time until the chip failed. We held
the voltage for VDD(core) constant at A2. Once the chip
failed, we noted the VDD(I/O) as the I/O breakdown voltage
value B1, then labeled and stored the failed unit. Again,
we verified the test procedure on another KGU.
March–April 2006
Set VDD(core) and VDD(I/O) to
maximum specification.
Run pattern list chosen
for HVST on chip.
Add 100 mV to both
VDD(core) and VDD(I/O).
No
Did
the chip
fail?
Yes
Note voltages of VDD(I/O) and VDD(core)
as A1 and A2 and save failed unit.
Figure 4. Test flow for identifying initial breakdown voltages.
Set VDD(I/O) and VDD(core) to 300 mV
below A1 and A2 respectively.
Run pattern list chosen
for HVST on chip.
Add 100 mV
to VDD(I/O).
No
Did
the chip
fail?
Yes
Note VDD(I/O) as B1 and save failed unit.
Figure 5. Test flow for finding the I/O breakdown voltage.
The third step was to identify the core breakdown
voltage (see Figure 6). We set the core voltage supply
to 300 mV below the initial breakdown level A2, and we
set VDD(I/O) to 300 mV below the I/O breakdown voltage
B1. We then incremented the VDD(core) level by 100 mV
until the KGU failed. We marked the core voltage of the
device under test at the time of failure as the core breakdown voltage B2. We then repeated the entire flow on
another unit to verify the result.
With both the I/O and core breakdown voltages
found (B1 and B2, respectively), our next step was to
verify the reliability of these voltage levels by testing
their repeatability (see Figure 7). We set both supply
voltages to 300 mV below their found breakdown
93
Latent-Defect Screening
Set VDD(core) to 300 mV below A2.
Set VDD(I/O) to 300 mV below B1.
Run pattern list chosen
for HVST on chip.
Add 100 mV to V.
Did
the chip
fail?
No
Yes
Note VDD(core) as B2 and save failed unit.
Figure 6. Test flow for finding the core breakdown voltage.
Set VDD(I/O) and VDD(core) to 300 mV
below their respective
breakdown voltages, B1 and B2.
Run pattern list chosen for
HVST on chip on set of ICs.
Add 50 mV
to VDD(core).
Add 50 mV
to VDD(I/O).
Core
I/O
Testing for
core or I/O
voltage?
No
Did
any chip
fail?
Yes
Note voltage
level and save failed units.
Figure 7. Test flow for checking the voltage levels’
repeatability.
voltages B 1 and B 2 and applied the list of HVST test
patterns.
When testing for the core voltage repeatability, we
held the VDD(I/O) level constant and incremented the
VDD(core) level by 50 mV until failure occurred. Similarly,
to test for I/O voltage repeatability, we left the VDD(core)
level unchanged while incrementing the VDD(I/O) level by
50 mV until failure occurred. We used a sample IC set
94
for both these tests. We segregated the failed units and
noted the voltage levels at the times of failure. If the data
showed that repeatability was unsatisfactory, we repeated the breakdown voltage characterization for a new
set of KGUs.
Once we had identified repeatable breakdown voltages, we modified the test program to run the test patterns with the HVST voltages at 80% of the breakdown
levels for VDD(core) and VDD(I/O). To verify the HVST pattern
(Figure 7), we used a set of three wafer lots (200 units
each). We executed the HVST pattern repeatedly on all
600 units and segregated and verified the rejects. We
repeated this procedure until the entire set passed three
consecutive cycles without a single reject.
In other words, if the sample set passed after X executions of HVST, and also after (X + 1) and (X + 2) executions, this let us establish the repetition for the HVST
pattern as X times—the first of the three consecutive
reject-free passes on the entire set.
Stage 4: Plan the burn-in experiment
In industry, burn-in normally takes place in multiple
time intervals, with each interval representing a fraction of the total burn-in process. Each interval allows
collection of data that then determines the suitable
number of burn-in hours at the newly specified conditions. After each burn-in interval, a high-temperature
test (called a hot test) must take place, and all failures
must be verified using the specifications datasheet.
Devices that meet the data specifications but still fail
(nondevice-related failures) are not counted toward
the number of failures in the experiment; we subtract
them from the sample size for that interval. Examples
of such failures include damaged or missing balls (contact terminals), count variance (missing devices), and
situations resulting from a compromised manufacturing process (for example, missing wire-bonding stemming from assembly process faults).
Figure 8 shows the burn-in intervals and the tests carried out during our experiments. The shaded boxes represent intervals of burn-in time, and arrows indicate
when tests occurred.
For reliable Weibull analysis, we needed post-burnin hot tests at two intervals before the target total burnin time tBI and at one interval after it.13 In our research,
because we had identified tBI as 3 hours, we chose
burn-in cycles that ended at 0.75 hours and 1.5 hours
(creating two intervals before the desired tBI); 3 hours
(the target tBI); and 6 hours (creating one interval after
the tBI).
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After the third hour of
HVST
Post hot
Post hot
Post test 3, room test
Post hot
burn-in, we took a data
test
test 1
test 2
and cold test
test 4
log for the dc parametric
(static currents and volt0.75 hrs
0.75 hrs
1.5 hrs
3 hrs
age levels), ac parametric
(timing parameters), and
Total hours
0.75
1.5
3
6
functional tests performed
at room, hot, and cold Figure 8. Burn-in performed in intervals.
temperatures. The data
log allows cross-checking
of various testing parameters, so it is especially impor- after the 48-hour proof burn-in (H13 and H14), which
tant in the event of an anomaly. These three tests are indicates that our reduced-time burn-in did not reduce
similar to the production tests that the devices normal- reliability, and that the failure rate is within market
ly undergo after burn-in and prior to shipping.
requirements.
The outcome of Stage 4 was the Weibull analysis
To justify our application of HVST, we had to conwith HVST experimental flow, shown in Figure 9.
firm its effectiveness and reliability. Thus, we compared
To provide experimental proof of our approach, we the results from point H1 of the experimental burn-in
tested a sample size of three wafer lots (about 3,000 flow with those from point B2 of the control flow (Figure
units per wafer lot). First, we executed hot, room-tem- 9). Table 5 shows the comparison between the yields
perature, and cold tests to screen out all defective units; provided by the experimental flow and the control flow,
this ensured that any failures that occurred during tests for room-temperature tests.
H1 to H14 (see Figure 9) would be true failures induced
The room-temperature test combined with HVST
by the HVST and burn-in. The aim of this experiment screened out 1.13% more rejects than the room-temperwas to determine the suitable burn-in duration and con- ature test after the traditional 12-hour burn-in. In other
ditions to use for production testing of this device.
words, applying HVST can be as effective in screening
So that we could establish a standard for results com- out weak infant devices as a 12-hour burn-in. For the hot
parison, we designated half the units from each wafer test, the yield difference between the control flow (B3)
lot as a control batch. These units underwent process- and the experimental flow (H3) for the 9,000 units used
ing in accordance with the control (old) testing flow, in this experiment was only 0.25% (see Table 5).
while the remaining units underwent our HVST and
The similarity between the room-temperature and
Weibull experimental flow. The control units underwent hot tests is a good indication that while the HVST
the 12-hour burn-in from the old test procedure; the stressed the devices well enough to screen out weak
HVST and Weibull units followed the burn-in intervals infants, it did not damage good units. In short, the test
shown in Figure 8, under burn-in conditions based on results show that the HVST program is both effective
calculations we’ll explain later.
and reliable.
To ensure that our new burn-in conditions were reliable, we added a 48-hour proof-of-concept burn-in after- Stage 6: Apply Weibull statistical technique to
ward as a check. If we observed additional failures after analyze the data
the 48-hour burn-in, we would know that our new burnOur next step was to use our experimental results and
in conditions were not sufficiently reliable and that we Weibull distribution to study the early life failure rate
would have to revise them. If we saw no additional fall- (ELFR) against the burn-in duration. Using the linear recouts after the 48-hour proof burn-in, we would know tification method, we can rewrite the Weibull cumulathat we could use the results of tests H1 to H11 for fur- tive density function (CDF) in linearized form, as
ther data analysis.
ln{–ln[1 –F(t)]} = m ln(t) – m ln(c)
Stage 5: Validate HVST effectiveness
Our results, listed in Table 4, cover the three random
wafer lots of 3,000 units each, totaling 9,000 units. (To
maintain confidentiality, we discuss only percentage
yields in this article.) We observed no additional fallout
March–April 2006
By using y = ln{–ln[1 – F(t)]} and x = ln(t), we can
use a least-squares fit to estimate the Weibull parameters. (This model is an effective and relatively simple
means of modeling the complex nature of product fail-
95
Latent-Defect Screening
Start
1
Hot test
2
Room test
3
Cold test
B1
B2
B3
B4
HVST effectiveness study
H1
Room HVST test
H2
1-hour burn-in (new conditions)
H3
Hot test 1
H4
1-hour burn-in (new conditions)
H5
Hot test 2
H6
1-hour burn-in (new conditions)
H7
Hot test 3
H8
3-hour burn-in (new conditions)
H9
Hot test 4
H10
Room test
H11
Cold test
H12
48-hour burn-in (old conditions)
H13
Hot test
H14
Room test
12-hour burn-in
Room test
Hot test
Weibull analysis
Cold test
Stop
Burn-in control flow
HVST and Weibull experimental flow
Figure 9. Burn-in reduction using Weibull statistical analysis and HVST.
ures.14) Using the expression for the linearized Weibull
CDF, we can find the slope parameter c as
⎡1
c=⎢
⎢⎣ n
1
n
⎤m
ri + 1 t im ⎥
⎥⎦
∑( )
i =1
Here, n is the number of intervals, r is the censor, t is
the time of failure, and m is the scale parameter. We can
present m as satisfying the equation
n
1 1
+
m n
∑
i =1
∑( r +1)t
i
n
log x i −
logt i
i =1
=0
n
∑( r +1)t
i
i =1
96
m
i
m
i
Once we find the parameters of the Weibull distribution best describing the statistics of the device’s failure
occurrence, we can calculate the estimated value of the
PPM parameter against burn-in time. The calculations
are based on the Weibull analysis readout collected
during the study.
We created an ELFR burn-in duration study graph
(Figure 10) by extrapolating the calculated Weibull distribution. This plot shows the ELFR achieved at various
durations of burn-in. The reduced burn-in process
changes the part’s PPM level. Specifically, the part’s
PPM level was reduced because of the increased acceleration factor.
Finally, we determined the new burn-in duration
based on predetermined criteria specific to the device,
IEEE Design & Test of Computers
such as PPM, confidence level, and duty cycle per
week. As Figure 10 shows, we can reduce the required
burn-in time by up to 90% and still achieve the same
PPM. This is an excellent outcome for the research,
showing that the HVST program can be highly effective
in screening out weak infant devices while providing a
very significant reduction of burn-in time.
Table 4. Average yield results: Traditional burn-in
compared to Weibull/HVST experimental testing.
Average yield of
Read point
three wafer lots (%)
Control flow
ACCELERATED TESTING is a vital part of ensuring prod-
B2
99.60
B3
99.96
B4
99.46
Experimental flow
Acknowledgments
This research resulted from an ongoing collaboration between Freescale
Semiconductor Malaysia and Monash
University Malaysia. We thank Monash
University for awarding the postgraduate
degree scholarship to Melanie Po-Leen
Ooi. We thank Freescale Semiconductor
Malaysia (formerly Motorola Semiconductor Malaysia) for the research opportunity, equipment, and resources.
March–April 2006
ELFR failure result (PPM)
uct reliability, and burn-in is one of the most popular
H1
98.47
techniques. However, although burn-in guarantees a
H3
99.71
degree of reliability and quality, it incurs high turnH5
99.71
around time and high cost. The burn-in reduction
H7
100.00
methodology that we researched and implemented
H9
99.77
shows that, at least for some devices, the use of HVST
H10
99.94
combined with Weibull statistical analysis can reduce
H11
99.77
burn-in time significantly without affecting reliability
H13
100.00
and quality.
H14
100.00
Aiming to further reduce manufacturing costs, the
wafer-level test and burn-in (WLTB) approach has
been recently proposed.
Although initial steps
Table 5. Comparison between the control and experimental flow results to study the HVST effectiveness.
have already been taken
Test code
Test description
Average yield (%) Yield difference (%)
toward development of
WLTB systems, this techB2
Control flow, room tests
99.60
nology is still in its infancy
H1
Experimental flow, HVST, room tests
98.47
1.13
in terms of available
B3
Control flow, hot tests
99.96
industry standards and
H3
Experimental flow, HVST, hot tests
99.71
0.25
equipment. With the successful reduction of the
burn-in duration by 90% using Weibull
2,500
analysis with HVST, and with the initial
actions undertaken to move HVST and
burn-in testing to the wafer level, we are
2,000
one step closer to dramatically reducing
or even eliminating burn-in for packagelevel testing.
■
1,500
1,000
ELFR of traditional/old burn-in conditions (PPM)
500
ELFR of desired/new burn-in conditions
0
0
2
4
6
8
10
12
14
Burn-in duration (hours)
Figure 10. ELFR versus burn-in duration.
97
Latent-Defect Screening
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98
Direct questions and comments about this article
to Zainal Abu Kassim, Freescale Semiconductor
Malaysia Sdn. Bhd., No. 2 Jalan SS 8/2, Free Industrial
Zone Sungei Way, 47300 Petaling Jaya, Selangor D.E.,
Malaysia; zainal.abukassim@freescale.com.
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